1. Field of the Invention
The present invention relates to a semiconductor device, an electrical device and a control signal generation method, that generate control signals.
2. Description of the Related Art
Generally, brushless DC motors are often employed as fan motors. Such brushless DC motors generally are configured by a number of coil(s), and a rotor to which a permanent magnet is attached, with the rotor rotated by magnetization of the coils by supply of current thereto. Namely, the current in the coil is controlled according to the rotation position of the rotor, and the rotor is rotated by changing a magnetic field. A method of applying a constant voltage to both ends of the coil is suggested as one method of making current flow in and magnetizing the coil. In such a method, the rotation speed is controlled according to the voltage level applied. In contrast thereto, as a more general method, a method of applying a voltage using Pulse Width Modulation (PWM) is suggested to raise electromotive force efficiency. In such a method, the rotation speed is controlled by the duty ratio of the PWM signal.
A Hall device and back electromotive force during switching are employed to detect the rotation position of the rotor. A motor drive circuit switches polarity of voltage applied to the coil based on a timing from detecting a Hall signal or back electromotive force. In order to reduce motor drive noise in the vicinity of such a switching timing, a motor drive circuit that performs soft switching is employed to gently change the voltage and polarity applied to the coil. The effectiveness of motor drive noise reduction varies depending on characteristics such as the start timing of soft switching and the manner in which voltage is changed after the start of soft switching. A motor drive circuit is accordingly matched to the type of motor actually being employed and to conditions of use in order to minimize drive noise.
For example, in Japanese Patent Application Laid-Open (JP-A) No. 2007-174778, technology for driving is described that sets the soft switching start position at 62.5%, 75% or 87.5% of a half cycle of a Hall device signal, with the remaining region from there onwards of 37.5%, 25% or 12.5% divided into 8 or 16 steps of gradually reducing duty of a PWM signal applied to a coil.
Further, in JP-A No. 2011-19386, a technology that enables selecting a voltage change cycle (voltage change slope) during soft switching execution, and the soft switching execution period, by using a pre-set constant value, is disclosed.
Further, for example, JP-A No. 2006-174017 discloses a technology that manages a table of change amounts of duty ratio. In this technology, a program pre-written to ROM reads values from a table, and generates a PWM signal under control of the program configured from a combination of sub-routines.
However, whichever of the above technologies is employed, flexible response still may not be made, in cases such as when one motor is replaced by a motor with different characteristics.
For example, in the technology described in JP-A No. 2007-174778, the soft switching start position (62.5%, 75% or 87.5% of a half cycle of a Hall device signal) and the duty change steps of the PWM signal during soft switching execution (8 steps or 16 steps) may be changed. However, it is necessary to change hardware (the motor drive circuit) in order to perform such change. Moreover, since there are only limited selectable positions, it may not be possible to set optimal characteristics for many motors.
For example, in the technology described in JP-A No. 2011-19386, the soft switching execution period may be changed by changing the values of the pre-set constant. However, start position of the soft switching may not be changed. Consequently, it is not possible to set optimal characteristics for many motors.
However, in the technology described for example in JP-A No. 2006-174017, High/Low switching over of each pulse of a PWM signal is implemented by interruption processing. Thus, in such technology, the burden may be increased by the software interruption processing, with the possibility arising that the processor is unable to keep up with the processing.